css: Fix erroneous non-secure RAM base address/size for SGI-575

SGI-575's NSRAM is neither in the same place nor the same size as Juno's.

Change-Id: Id6d692e9c7e9c1360014bb525eda966ebe29c823
Signed-off-by: Chris Kay <[email protected]>

diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index deea1bb44539a787003a55db5e4594ef72e2927b..275e591ada079c8dc4afa6d8821318bff323c1c0 100644 (file)
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -22,9 +22,6 @@
 #define CSS_DEVICE_BASE                        0x20000000
 #define CSS_DEVICE_SIZE                        0x0e000000
 
-#define NSRAM_BASE                     0x2e000000
-#define NSRAM_SIZE                     0x00008000
-
 /* System Security Control Registers */
 #define SSC_REG_BASE                   0x2a420000
 #define SSC_GPRETN                     (SSC_REG_BASE + 0x030)

diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index c8349413e88df7c88815af74f736fec1d57dfe24..e616e1fcfecc244bd147a4d3d33b572263c4d80c 100644 (file)
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -56,6 +56,9 @@
 /* Use the bypass address */
 #define PLAT_ARM_TRUSTED_ROM_BASE      V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
 
+#define NSRAM_BASE                     0x2e000000
+#define NSRAM_SIZE                     0x00008000      /* 32KB */
+
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME   0xc0000000
 

diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h
index 62f4059999d0bc3281a5c7d1af7c6c94cdbccfeb..49a33ad6c371a2d707bc2532cbad1ba94422f8f9 100644 (file)
--- a/plat/arm/css/sgi/include/platform_def.h
+++ b/plat/arm/css/sgi/include/platform_def.h
@@ -52,6 +52,9 @@
 #define PLAT_ARM_TRUSTED_ROM_BASE      0x0
 #define PLAT_ARM_TRUSTED_ROM_SIZE      0x00080000      /* 512KB */
 
+#define PLAT_ARM_NSRAM_BASE            0x06000000
+#define PLAT_ARM_NSRAM_SIZE            0x00080000      /* 512KB */
+
 #define PLAT_MAX_PWR_LVL               1
 
 #define PLAT_ARM_G1S_IRQS              ARM_G1S_IRQS,                   \